The present invention relates to fabricating submicron semiconductor devices, and more particularly to fabricating a submicron semiconductor device having a self-aligned channel stop region using a trim and etch method.
During the manufacturing of integrated circuit devices, the devices are isolated from one another through a combination of a thick field oxide (FOX) and channel doping. The area required for the isolation region is a limitation to high packing density. The isolation spacing required is due in part to the process used to fabricate the devices.
As device geometry decreases past submicron size, conventional fabrication processes reach the limit of their effectiveness. For example, compare a conventional process flow that might be used to fabricate a CMOS (complementary metal oxide) circuit having a feature of size 1.25-2 microns with a conventional process that might be used for a circuit having a feature of size 0.8 microns.
The process for fabricating the 1.25-2 micron device begins by covering the substrate with a thin layer of nitride in a pattern that defines active device and FOX regions. Thereafter, the substrate in the field regions is selectively implanted with a channel stop dopant, such as boron, during a channel stop implant process. The field oxide is then grown during a LOCOS (LOCal Oxidation of Silicon) process to form the FOX regions. During this process, the channel stops are self-aligned to the FOX regions. The nitride layer is then removed from the active regions, and a gate oxide is grown followed by a deposition of polysilicon for the gate layer.
Performing the LOCOS process after the channel implant causes thermal diffusion of the dopant towards the active areas due to the growth of the FOX regions. Because the devices are so large, however, the amount of thermal diffusion is relatively small when compared to the spacing between the devices. Consequently, the diffusion caused during this process does not negatively affect such large devices. The process is inappropriate, however, for smaller devices because due to denser spacing of smaller devices, the dopant from the FOX regions encroaches the active areas and comprises the devices.
FIGS. 1A-1C are cross sectional views a substrate showing an improved process flow that might be used to fabricate a CMOS circuit having a feature of size of approximately 0.8 microns, for example. First, a layer of nitride 10 is deposited on a substrate 12 and then etched such that the nitride 10 remains only over the active regions, as shown in FIG. 1A. FIG. 1B shows that a thermal-oxidation step is then performed to grow the field oxide (FOX) regions 14 between the active regions. FIG. 1C shows that after the FOX regions 14 are grown, the nitride 10 is selectively removed and a photo resist is patterned over the remaining nitrite layers to act as a mask 16 for a channel stop implant process, shown by the arrows.
Although this process is an improvement over older techniques, it suffers from lithographic resist tolerance limitations. To provide proper channel widths between the active areas, a relatively thick resist mask must be used that must be patterned with tolerances on the order of 140 nanometers or 0.14 microns. To prevent encroachment of the oxide and the dopant to the closely spaced nitride layers over the active areas, the resist can only be misaligned from the nitride layers by plus or minus approximately 100 nanometers, or 0.1 microns. Patterning such a thick layer of resist at such exacting tolerances is extremely difficult. Furthermore, in this process, the FOX regions and the channel stops are not self-aligned.
Accordingly, what is needed is an improved isolation process that is suitable for semiconductor devices having feature sizes of approximately 0.3 microns. The present invention addresses such a need.
A submicron semiconductor device having a self-aligned channel stop region, and a method for fabricating the semiconductor device using a trim and etch is disclosed. The submicron semiconductor device includes a plurality of active regions separated by insulating regions. The method for fabricating the device includes depositing a nitride over a substrate and selectively covering the active regions with a mask, wherein the mask extends beyond boundaries of the active regions to narrow the width of the insulating regions. Thereafter, a channel stop implant is performed to form channel stops. The mask is then trimmed to the boundaries of the active regions after formation of the channel stops, followed by etching the nitride in exposed areas of the mask. Field oxide is then grown in the insulating regions, whereby the field oxide is self-aligned to the channel stops.
According to the present invention, enlarging the nitride mask to narrow the insulating regions for the channel stop implant effectively reduces the amount that the dopant that diffuses during the LOCOS process, which therefore allows the fabrication of smaller devices.